Univers COVER: SW/HW co-verification

General Description

Univers COVER is the development tool for creating and verifying systems which include one or more CPU's and HDL designs.

The Univers COVER IDE combines the following items to one tool:
One or more CPU's models (Instruction Set Simulators)
API to include C++ models (peripherals, data analysis, ...)
HDL compiler & simulator: Verilog or VHDL or both.
Many design views and specific windows, see more below.

Univers COVER is the ideal solution to have the System Engineer, Software Engineer and Hardware Engineers work together with one and the same tool. The hardware engineer can use the Hardware Abstraction Layer (HAL) software immediately to verify the hardware from the CPU level instead of using a limited bus functional model. The HAL software is tested at the same time. Software views can be created by each engineer to ease debugging. For high speed system level development purposes a C++ model is attached to the ISS. This model can be created before or after the creation of the HDL design, dependent on the project requirements. These models provide full visibility and controllability and they can include additional features such as graphical LCD output.

The tools are build for user convenience, providing full controllability and visibility of a complete system. User convenience includes also providing a short iteration cycles to developers. The iteration cycle is within SW/HW co-verification dominated by the speed of the digital simulator. Adveda has succeeded to build an ultra fast digital simulator, extremely suitable to be used for SW/HW co-verification. This simulator supports many unique features, while maintaining the speed. Compared to mainstream digital simulators the Adveda simulator is between 5x to 100x faster, dependent on the coding style and type of design.

 

Features

True multi core development and verification environment
Fast cycle-accurate Instruction Set Simulators
Ultra Fast HDL simulation (Verilog/VHDL)
Complete Integrated Development Environment
Automated flow for multi-core SoC projects
Open debug-API for easy integration
Extensive and unique debug features
Automatic embedded OS support
Multi target (ISS, RTL, HW)
 

Detailed info

Additional Info: ISS specific:
Multicore simulation and verification Application window
System level exploration & development Disassembly window
Modelling capabilities / Peripheral models Register window
Peripherals (standard available) Memory window
Breakpoints Variable/Watch/Stack window
Multi clock systems Modules window
Step & Compare Interrupt/DMA window
  Select Signals window
Univers Options: Signals window
Performance profiler  
HDL navigator HDL specific:
  Model window
  Register window
  Select Signals window
  Signals window
   
 

More info

 

If you require more information you can ask Adveda, click here.
For evaluation purposes a full evaluation version of the Univers tools is available.

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