Step and Compare

General Description

Univers is capable of handling multiple modules, therefore it is possible to incorporate two different implementations of the same functionality. Assume a fast executing model of a CPU is available as a result of architectural design exploration. During the implementation of the CPU in HDL code, you can verify the HDL implementation against the model. This serves two purposes:
1. A continuous verification mechanism is available during development
2. Both implementations continue to reflect the same functionality

A cross-check between two implementations is also valuable to validate IP models against available other implementations.

The Step and Compare function performs user defined checks on resources after each simulation step. These resources are CPU registers and/or memory areas. You can chose to include or exclude the timing check as part of the functional check. Test coverage is maintained and provides information about untested areas of the design.

A normal program uses often only a very limited set of possible instructions, especially when the code is compiled by a C compiler. To test each individual instruction and to test random sequences of instructions a user controlled pseudo-random test generator is integrated in Univers. Using this test generator boosts the test coverage dramatically.



User definable checks after each simulation step
Selections between fully functional checks or functional + timing checks

Test coverage window
User controlled pseudo-random test generator

User defined set of adjacent, N-times executed, tests
Pre defined load of memory areas
Include compiled source code to the tests

Reports of implementation differences


For all your high-speed SW/HW co-verification tools
Copyright 2002-2017 Adveda B.V. - E-mail: - Tel: +31 624 504 862