Signals window

General Description

The signals window shows time related waveforms of signals. Signals from different modules (Instruction Set Simulators and HDL designs) can be viewed in the same window to observe time relationships. In front of each signal the module identifier is placed. In the figure below you can observe the program counter of an ARM (core 1) and of a NIOS II CPU (core 2). Hovering with the mouse above a signal provides additional information: for a program counter also the data pointed by the program counter and the disassembly of that data is presented.

Signals from an ISS can be directly related to HDL signals during execution of code. Many features are included to highlight information of particular interest.

A Value Change Dump (VCD) file can be loaded to verify a design against a given set of waveforms, which may be derived from a model or from another digital simulator. Signals which are part of the Signals window are automatically connected to their counterpart in the VCD file. For such signals two traces are drawn, the VCD trace and the trace derived from the current simulation.

Program flow:
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Features

Signals from different modules (CPU's & HDL designs) are viewed in the same window
Multiple signal windows can be used
View waveform data, highlight specified special cases
View program flow or view execution in specified memory areas
View stall cycles
Zoom functions (specify X-axis time, zoom in/out, zoom area)
Simulation control buttons
Cross-Verify 2 implementations of a design, Compare traces against VCD traces
Log trace data to file
 
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