CPU models: Instruction Set Simulators (ISS)

General Description

These processor models are developed by Adveda. The creation of these models has proven to be much faster (8x..10x) than a development in C++. They are also better to maintain, since they are described at a high abstraction level.

CPU models include:
Disassembly, Instruction timing, Program flow info,
Register views, Stack views,
Basic memory models,
Dependent on the CPU: Dynamic Configuration
 

CPU models (ISS)

A growing number of Instruction Set Simulators is available. The list below provides an impression about the variety of different processor models:
A2P (Advanced Architects)
ARM
ARM Cortex family
MIPS
TI DaVinci
TI TMS320-6000 family
Power PC
NIOS II
MicroBlaze
AVR
8051
PIC
R.E.A.L DSP
Your proprietary CPU
 

ISS development

Adveda can develop an ISS of almost any processor. We have successfully build such models for small microcontrollers but also for large and complicated vector processors. These instruction Set Simulators typically run at a speed up to 10 MHz. They fit immediately in the Univers environment, where Univers provides the controllability and visibility of the virtual system which includes this ISS.

Quality and Accuracy:
Special dedicated developed tools guarantee high quality by performing script-controlled pseudo-random tests where the model simulates in parallel with the golden reference of the CPU. Functionality as well as timing is verified this way.

Building a dedicated ISS:
If you have developed your own processor, we can develop the ISS for that processor in a relative short period of time. The second benefit is that you have immediately a very sophisticated development and simulation tool for yourself and for your customers available for a very affordable price with a perfect Return On Investment.
Ask for a quotation.

 

More info

 

If you require more information you can ask Adveda, click here.
For evaluation purposes a full evaluation version of the Univers tools is available.

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