| The Univers ISS
(Instruction Set Simulator) model of the NIOS II processor
includes:
Full instruction set of the e, s and f version
of the NIOS II CPU
Full support for RTL custom instructions
Automatically ISS configuration by parsing the
Altera .ptf project file
Basic timing model for instruction execution for
e, s and f version
Branch prediction
Register and Memory windows
Functional bus models for:
Avalon Master Instruction bus
Avalon Master Data bus
Custom Instruction bus
Instruction cache
Data cache
Adveda’s
development, simulation and
debug tools offer the
designer full visibility and full
controllability of the design.
Some of the unique
features: |
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The accurate Static/Dynamic
Profiler analyzes the application code without
code changes. Real ISS timing data is used
without using timers or other sampling
techniques to present an accurate results. The
results are available in ASCII tabular format or
fully graphical, including individual stall
reasons on procedure and instruction level
basis. The
Profiler provides the correct data to make
design decisions such as:
- Which part of the software is a candidate to
be transferred from software to hardware to
boost the application. In this way the profiler
is a huge add on for Altera's C2H.
- How can I optimize this critical part of the
code, which instructions contribute most to
additional stall cycles.
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When your
design contains HDL code you can take advantage
of the ultra fast HDL simulator. This simulator
is factors faster than mainstraim digital
simulators. The HDL simulator connects
without any overhead to our Instruction Set
Simulators.
Verilog and VHDL is supported.
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Simultaneous
simulation (and debugging) of more NIOS
processors (or other processors, eg an ARM7TDMI)
in multi-processor applications including all
hardware-peripherals (Verilog or VHDL code) in one
unified simulation environment.
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If a location
(register, memory cell or variable) with an
unexpected value is found during debugging,
Univers will identify the
responsible source code, leaving no room
for speculation and saving
valuable time.
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Unlimited breakpoints can be set at any place in the
source code, assembly code, registers or memory
locations without affecting the simulation
speed and will stop all processors at
exactly the same time.
Breakpoints can individually be enabled or
disabled. |
